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| this is information on a product in full production. september 2013 docid023902 rev 4 1/60 1 L99CL01XP 8 channel high-side led driver for automotive applications datasheet - production data features ? octal fully protected high-side switches with programmable overcurrent threshold and rdson ? split supply for flex ible application assignment (6 v to 24v) ? spi communication interface with daisy chain capability ? digital diagnosis individually for each switch ? analogue current sense output with spi programmable multiplexer ? integrated synchronous pwm module with programmable phase shift, pulse skipping feature and quick access via direct drive pins ? improved emc behavior by phase shift control and output edge shaping ? limp home function with 6 independent direct drive pins ? integrated fail mode handling ? ultra low power mode (< 5 a max at 25c) applications ? automotive inte rior lighting ? automotive exterior lighting description the L99CL01XP is designed to provide a cost effective solution for exterior and interior automotive lighting applications with leds. * $ 3 * & ) 7 powersso-36 table 1. device summary package order code tube tape and real powersso-36 root part number 1 L99CL01XPtr www.st.com
contents L99CL01XP 2/60 docid023902 rev 4 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 power supply (vs, gnd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2 vdd (logic interface supply voltage) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 enable (active high) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 switch supply terminals (vsa, vsb, vsc and vsd) . . . . . . . . . . . . . . . . .11 2.2 power outputs [out1 ~ out8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.3 current sense (cs) ? analog diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 control inputs (in1, in2, in3, in5, in6, in7) . . . . . . . . . . . . . . . . . . . . . . 12 2.5 pwmclk input / wake output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5.1 pwmclk input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5.2 wake output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6 limp input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.7 control, protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.7.1 smart switches and gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.7.2 pwm module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.7.3 overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.7.4 external resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.7.5 channel voltage level comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.7.6 device protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 spi communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1.1 csn (chip select (active low)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1.2 sck (serial input clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1.3 sdi (serial data input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1.4 sdo (serial data output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1.5 control data registers (cdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1.6 status data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.2.1 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.2.2 wake up and operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 docid023902 rev 4 3/60 L99CL01XP contents 3.2.3 cold start ? power up reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.2.4 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.2.5 fail mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.2.6 warm start ? (transition from failmode to normal over internal reset) 44 4 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.1 absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.1 powersso-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.1 ecopack ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.2 powersso-36? mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.3 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 list of tables L99CL01XP 4/60 docid023902 rev 4 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. pwm mode selection for outx (x = 1, 2, 3, 5, 6 or 7) when inx is disabled . . . . . . . . . . . 14 table 4. pwm mode selection for outx (x = 1, 2, 3, 5, 6 or 7) when inx is enabled and inx = 0 . . 15 table 5. pwm mode selection for outx (x = 1, 2, 3, 5, 6 or 7) when inx is enabled and inx = 1 . . 15 table 6. examples of settings for inselx[1:0] and pwmselx[1:0] resulting in outx states, which are independent from inx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 7. examples of settings for inselx[1:0] and pwmselx[1:0] resulting in outx states, which are dependent from inx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 8. pwm mode selection for out4 and out8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 9. duty cycle selection (psf enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 10. error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 11. cdr registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 12. control data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 13. sdr registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 14. status data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 15. mapping between the input pins and the outputs in fail mode. . . . . . . . . . . . . . . . . . . . . . 42 table 16. events leading to fail mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 17. control registers in fail mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 18. absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 19. temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 20. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 21. digital timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 22. electrical characteristics (logic + inputs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 23. dynamic characteristics (spi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 24. switching (v s =12v; t j = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 25. electrical characteristics (out1 - out8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 table 26. electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 27. electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 28. electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 29. powersso-36? mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 30. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 docid023902 rev 4 5/60 L99CL01XP list of figures list of figures figure 1. application block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 5. toggle signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 6. fail mode status diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 7. reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 8. spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 9. powersso-36 pc board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 10. r thj-amb vs pcb copper area in open box free air condition (one channel on) . . . . . . . . . 54 figure 11. powersso-36? package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 12. powersso-36 tube shipment (no su ffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 13. powersso-36 tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 block diagram and pin description L99CL01XP 6/60 docid023902 rev 4 1 block diagram and pin description figure 1. application block diagram 6 ' , 6 3 , & 2 1 7 5 2 / / 2 * , & * 1 ' & 6 1 6 & . 6 ' 2 9 e d w 3 : 0 & / . , u h i 9 u h j 9 r u 9 0 l f u r f r q w u r o o h u & 6 9 ' ' 9 ' ' n n n n n n n 9 e d w b 6 : , 7 & + b ( 1 $ % / ( n : $ . ( / , 0 3 , 1 , 1 , 1 , 1 , 1 , 1 ) d l o 6 d y h / r j l f n 5 ( ; 7 n n n n n n n , 2 5 h i 9 6 p r q 9 l q w & r q w u r o ' l d j q r v l v & x u u h q w 6 h q v h 2 8 7 2 8 7 9 6 $ 2 8 7 2 8 7 9 6 % 2 8 7 2 8 7 9 6 & 2 8 7 2 8 7 9 6 ' 9 6 5 5 9 e d w b 6 : , 7 & + b 5 5 9 e d w b 6 : , 7 & + b 5 5 9 e d w b 6 : , 7 & + b 5 5 9 e d w * $ 3 * & ) 7 docid023902 rev 4 7/60 L99CL01XP block diagram and pin description figure 2. device block diagram / 2 * , & & 6 1 6 ' 2 6 ' , 6 & . 3 0 : & / . ( 1 $ % / ( / , 0 3 , 1 , 1 , 1 , 1 2 8 7 2 8 7 2 8 7 9 6 9 5 ( * 9 ' ' i d l o g h w 9 ' ' 2 8 7 9 6 $ 9 6 ' 9 6 i d l o g h w 9 6 8 3 $ i d l o g h w = d s s l q j 9 , 1 7 ' 2 6 & 0 8 ; & 6 * 1 ' 5 ( ; 7 s d g v j d w h g u l y h v o r s h f r q w u r o r s h q o r d g r y h u f x u u h q w 2 8 7 j d w h g u l y h v o r s h f r q w u r o r s h q o r d g r y h u f x u u h q w r y h u w h p s 3 2 5 % d q g j % , $ 6 8 , f r q y 8 u h i , u h i % , $ 6 u h i 2 8 7 2 8 7 2 8 7 2 8 7 2 8 7 2 8 7 2 8 7 2 8 7 2 8 7 2 8 7 2 8 7 v w d w x v v w d w x v v w d w x v v w d w x v v w d w x v v w d w x v v w d w x v v w d w x v 1 5 ( 6 6 3 , 3 : 0 ) $ , / 6 $ 9 ( ' , $ * 9 ' ' 5 h y 3 u r w ( 1 ( 1 ( 1 ( 1 ( 1 ( 1 ( 1 9 ' ' ( 1 s d g v s d g v , 1 , 1 s d g v ( 1 & / . 9 l q w h u q : $ . ( 9 6 % s d g v 9 6 & s d g v 9 6 8 3 [ i d l o g h w 9 6 % 9 6 & 9 6 ' * $ 3 * & ) 7 block diagram and pin description L99CL01XP 8/60 docid023902 rev 4 figure 3. configuration diagram (top view) table 2. pin function pin symbol function 1,18 gnd ground: this terminal is the ground for the logic and analogue circuitry of the device. 2rext external resistor: the resistor is used to improve internal current precision. 3vdd logic supply voltage: spi and logic i/o structure power supply. 4cs current sense output: this terminal is used to supply a current proportional to the output current in the power output stages. the selection of the output is spi programmable. 5 enable enable (active high): this input enables the device. after wakeup the internal configuration is in default state. the terminal has an internal pull down resistor. 6limp limp home input (active high): the fail mode of the component can be activated by logic [1] at this input. the limp state is internally filtered by a 10ms digital filter. this terminal has an internal pull down resistor. 7,8, 9,10, 11,12 in1, in2, in3, in5, in6, in7 direct drive input 1,2,3,5,6,7: these inputs enable the device and are used to control the corresponding power outputs 1,2,3,5,6,7 in case of fail mode (direct drive). during normal mode the control of the outputs is spi programmab le. all input terminals have an internal pull down resistor. & 6 3 : 0 & / . * 1 ' & 6 1 9 6 % * 1 ' 5 ( ; 7 9 ' ' , 1 , 1 , 1 , 1 , 1 6 ' 2 6 ' , 6 & . / , 0 3 , 1 2 8 7 9 6 % 9 6 $ 9 6 $ 9 6 2 8 7 2 8 7 9 6 & 9 6 & 2 8 7 2 8 7 9 6 ' 9 6 ' 2 8 7 2 8 7 2 8 7 9 6 3 r z h u 6 6 2 ( 1 $ % / ( * $ 3 * & ) 7 docid023902 rev 4 9/60 L99CL01XP block diagram and pin description note: the heat slug is internally connected to gnd. 13 csn spi chip select input (active low): when this digital signal is logical [1], spi signals are ignored. asserting this terminal [0] an spi transaction starts. t he transaction is indicated as complete when this signal returns to [1]. this terminal has an internal pull up resistor. 14 sdo spi data-out: spi data is sent to the microcontroller by this terminal. this data output changes on the positive edge of sclk. when csn is [1], this terminal is at high impedance. 15 sdi spi data-in: this data input is sampled on the negativ e edge of the sck. the terminal has an internal pull down resistor. 16 sck spi clock input: this digital input terminal is connected to the controller providing the clock (up to 4mhz) for spi communication. the terminal has an internal pull down resistor. 17 pwmclk pwm clock input, (wake output if enable low): this clock defines the frequency of the internal generated pwm. the terminal has an internal pull down resistor. if enable is low, this pin is used as a wake output. this output indicates if another wakeup source, beside enabled, is active. 19, 22, 23, 26, 29, 32, 33, 36 out1 ~ out8 power output 1~8: fully protected high-side switches with individually programmable r dson and over current shutdown threshold. the output current is up to 1a per c hannel. however the total current of the device is limited due to the max power dissipation of the component and the total thermal resistance/capacitances of the pcb. the outputs out1~out3 and out5~out7 are controlled by the corresponding inputs in1, in2, in3, in5, in6, in7 during fail mode (out4 and out8 are off). during normal mode the outputs are controlle d by the internal pwm generator or the selected direct drive input. 20, 21 vsd supply voltage pins for outputs 7 and 8. pins must be tied together on pcb. 24, 25 vsc supply voltage pins for outputs 5 and 6. pins must be tied together on pcb. 27, 28 vs battery supply voltage: power supply terminal. 30, 31 vsb supply voltage pins for outputs 3 and 4. pins must be tied together on pcb. 34, 35 vsa supply voltage pins for outputs 1 and 2. pins must be tied together on pcb. table 2. pin function (continued) pin symbol function block diagram and pin description L99CL01XP 10/60 docid023902 rev 4 1.1 power supply (vs, gnd) the vs terminal is the power supply pin of the device and it is also used to supply the internal logic of the device. this pin is prot ected against reverse battery conditions without any external components, down to -24 v. overvoltage and undervoltage events on the vs pin are reported by the ovf, respectively the uvf status bits (refer to device status #2). once one of these events has occurred, the corresponding status bit is latched. the gnd is the signal ground and pow er ground terminal of the device. 1.2 vdd (logic interf ace supply voltage) the vdd is the logic interface supply voltage terminal, used to supply the spi communication interface and logic i/os of the device. the vdd is monitored by an internal circuitry. in case an under voltage condition is detected, the L99CL01XP enters the fail mode after the filter time t vdd_uv . 1.3 enable (active high) the enable is used to enable the dev ice by the microcontroller (normal mode). when the enable input is ? logic [0] the device is in standby mode (wake output enabled) ? logic [1] the device is in active mode (pwmclk input enabled) enable has an internal pull down resistor. please check for other wakeup sources the section 2.4: control inputs (in1, in2, in3, in5, in6, in7) . docid023902 rev 4 11/60 L99CL01XP functional description 2 functional description 2.1 switch supply terminal s (vsa, vsb, vsc and vsd) the device has four groups of output supplies in order to achieve flexible application fuse assignment. the vsa terminal is the drain (power supply pin) of the output switches 1 and 2, while vsb is the supply of switches 3 and 4, vsc is the supply of switch es 5 and 6 and vsd is the supply of switches 7 and 8. the su pply pins belonging to the same supply group must be connected together in order to ensure pr oper current capab ility for powermos devices. overvoltage and undervoltage ev ents on the vsx pins are repo rted by the corresponding ovf_x, respectively the uvf_x status bits (ref er to device status #3). once one of these events has occurred, the corresponding status bit is latched, the corresponding outputs are latched off and the outenx (see control register out enable, #10) is set to 0. the device is fully protected against loss of any supply terminal. 2.2 power outputs [out1 ~ out8] the power outputs are used to control led arrays with either integrated current source or series resistors. each output offers a fully protected p-chann el mosfet (programmable ron) driver with digital switch diagnosis and analogue current sense circuitry. paralleling of two or more outputs is possible in order to reduce power dissipation without rest riction in performance. the outputs are protected against: ? output over load and short circuit (incl. very low resistive short circuit and shorts with line inductance) ? overtemperature ? overvoltage/undervoltage the digital switch diagnosis by spi communication (see section 3.1.6: status data registers ) contains reporting of ? overcurrent shutdown status ? overtemperature shutdown status incl. over temperature warning status ? undervoltage/overvoltage status in case of undervoltage, thermal shutdown or overcurrent the corresponding out is switched off with edge shaping to reduce inter nal power dissipation in case of hard short. in normal mode, after a thermal shutdown, an overcurrent, an undervoltage or overvoltage at vsa, vsb, vsc or vsd, the co rresponding outputs are latched off unt il a read and clear command of the corresponding status register is sent. in fail mode, an overtemperature of an output le ads to a latch off, whereas, an auto restart strategy is implemented after an overcurrent, an undervoltag e or overvoltage at vsa, vsb, vsc or vsd. functional description L99CL01XP 12/60 docid023902 rev 4 2.3 current sense (cs) ? analog diagnosis the current sense terminal delivers a current which is proportional to the output current. depending on the programmed r dson [#9] (see section 3.1.5: contro l data registers (cdr) ) the ratio is defined to i out /1000 for 1 ? and i out /2000 for 600m ? . the mux[2:0] bits select which output channel is connected to the cs pin [#0:d7~d4] (see section 3.1.5: control data registers (cdr) ). fast output settling is provided in order to enable processing with synchronous sampling and peak detector as well as dia gnosis at very small duty cycle. 2.4 control inputs (in1, in 2, in3, in5, in6, in7) the control inputs are used to ? provide wakeup capability (see section 3.2.2: wake up and operating modes ) . ? directly control the correspondi ng outputs during fail mode (see section 3.2.5: fail mode ). ? control the outputs during normal mode, wh en the output control is enabled by spi register [#11, #12 and #13]. by default, the control inputs (inx) are disabled. for more detail see section 2.7.2: pwm module . the inputs have internal pull down resistors. 2.5 pwmclk input / wake output pin 2.5.1 pwmclk input when the device is enabled with the enable pin to logic ?1?, the pin acts as an input with which the pwm frequency is generated from pwmclk terminal by the integrated pwm module (see section 2.7.2: pwm module ). the clock input frequency is the factor 256 of the pwm switching frequency. (f pwm =100hz?400hz=>f clk =25.6khz?102.4khz). therefor e the internal pwm module provides an 8-bit resolution pwm. the pwm module is disabled in case of pwmc lk failure and the outputs are set according to the outxen control bits (control register #10). the status bit pclkf is set (status register #3, bit3). this bit is latched until a r ead and clear command is sent to this register. a pwmclk failure is detected when the frequency at the pwmclk input is lower than 5khz (t pos_lock_edge +1 - t pos_lock_edge > 1/5khz => failure). this failure is repor ted in the spi register [#1:d3] (see section 3.1.6: status data registers ). the input terminal has an internal pull down resistor. 2.5.2 wake output when the device is not enabled via the enable, th is pin is used as an output to indicate the wake state of the device which is related to the inx pins. [0] no wakeup source detected [1] inx wakeup source detected or 2sec wake timer running docid023902 rev 4 13/60 L99CL01XP functional description 2.6 limp input the fail mode (limp home mode) of the component is activated by this digital input port in addition to the internal fail mode detection circuit of the device (see section 3.2.5: fail mode ). the limp home mode is activated by a logic [1 ] signal at the input. during limp home mode the outputs are directly controlled by the inputs in1, in2, in3, in5, in6, in7. and the pwm module is disabled. the limp input has an internal pull down resistor. 2.7 control, protection and diagnosis 2.7.1 smart switches and gate drivers the smart switches are controlled by dedicated gate driver including: ? output pulse shaping ? overload protection incl. protection against low resistive short circuit and shorts with line inductance ? over temperature protection incl. over temperature warning signals the outputs are switched with active puls e shaping to provide an excellent emc performance of the system. therefore the output current of each driver is monitored by a feedback loop in order to control the switching speed of the output. thereby a compromise between edge shaping and propagation delay of the switch is necess ary to achieve low duty cycle values (3% < dc < 97% @ 250hz). 2.7.2 pwm module pwm control in order to minimize the microcontroller?s work load, a synchronous pwm module is integrated. the frequency and timing is derived from the pwmclock input (see section 2.5.1: pwmclk input ), the control of the pwm modul e is provided by spi and inx (see section : pwm control ) the smart switches can be controlled in the range of 0%...100% with a resolution of 1/256%. the value 00h in the individual and gl obal pwm registers refers to off state, the value ffh refers to 255/256 on state of the switches. the pwm timing includes 4 programmable switching phases (0, 90, 180 and 270). the phase can be controlled individually for each channel depending on th e channel control registers [#1~#8 d10~d9] the synchronization of the switching phases bet ween different devices is provided by the pwmsync bit in initialis ation register [#0:d8]. to guarantee a proper generation and smooth pwm duty cycle change via spi the duty cycle start point is defined by the internal pwm counter zero crossing. therefore every spi programmed duty cycle change and duty cycle source change will not take effect till the pwm counter zero crossing is reached (this strategy is also known as buffered pwm). setting the output to off or 100% on, the setting will occur immediat ely and independently from pwm counter. functional description L99CL01XP 14/60 docid023902 rev 4 for generation of output duty cycles close to 100% the pulse skipping feature is integrated (see pulse skipping feature ). the pwm module is disabled in case of ? fail mode (direct drive) ? clock input signal failure (controlled by pwmxen register) pwm module in normal mode with outenx bit = 1 this section describes the pwm control modes for out1-8, provided that the corresponding outenx bit is set (outx is enabled). if outenx bit = 0, the corresponding output is disabled. pwm control modes in normal mode fo r outx (x = 1, 2, 3, 5, 6 or 7) in normal mode, the state of the outx, x=1,2, 3,5,6 or 7 is determined by the combinations between inselx[1:0], pwmselx[1:0] and the state of inx, provided that outenx bit is set to 1. 3 cases must be considered: ? case 1: direct input inx is disabled (inselx[1:0] = [0,0]) ? case 2: direct input inx is enabled (inselx[1:0] ?? [0,0]) and inx = low ? case 3: direct input inx is enabled (inselx[1:0] ?? [0,0]) and inx = high case 1: inx is disabled: the output behaves according to the table 3 . ? individual pwm selected: in this mode the pwm control of the channels is provided individually for each channel by the corresponding channel co ntrol register [#1~#8:d7~d0]. ? gpwm1 selected: in this mode the pwm control of the switches is provided by the global pwm1 value [#14:d7~d0]. ? gpwm2 selected: in this mode the pwm control of the switches is provided by the global pwm2 value [#15:d7~d0]. ? 100% on selected: in this mode the output is fully on. ? off selected: in this mode the output is off. table 3. pwm mode selection for outx (x = 1, 2, 3, 5, 6 or 7) when inx is disabled outenx inx inselx1 inselx0 pwmselx1 pwmselx0 state of outx x = 1, 2, 3, 5, 6 or 7 1x (1) 1. x: do not care. 0 0 0 0 individual pwm 1x0 0 0 1 gpwm1 1x0 0 1 0 gpwm2 1 x 0 0 1 1 100% on docid023902 rev 4 15/60 L99CL01XP functional description case 2: direct input inx is enabled (inselx[1:0] ?? [0,0]) and inx = low in this case, the state of the output is indep endent from the settings of pwmselx[1:0]. it is determined only by setting of inselx[1:0] according to the table 4 . case 3: direct input inx is enabled (inselx[1:0] ? [0,0]) and inx = high if the direct input inx is high, the state of th e output is independent from the settings of inselx[1:0]. it is determined only by the setting of pwmselx[1:0] according to the table 5 . table 6 and table 7 show some examples of spi settings resulting in states of outx, which are independent ( table 6 ) or dependent ( table 7 ) from the levels at inx. other settings are possible. table 4. pwm mode selection for outx (x = 1, 2, 3, 5, 6 or 7) when inx is enabled and inx = 0 inx inselx1 inselx0 pwmselx1 pwmselx0 state of outx x = 1, 2, 3, 5, 6 or 7 low 0 1 x (1) 1. x: do not care. xgpwm1 low 1 0 x x gpwm2 low 1 1 x x off table 5. pwm mode selection for outx (x = 1, 2, 3, 5, 6 or 7) when inx is enabled and inx = 1 outxen inx inselx1 insel x0 pwmselx1 pwmselx0 state of outx x = 1, 2, 3, 5, 6 or 7 1 high x (1) 1. x: do not care, provided that inselx[1:0] is different from [0,0] x 0 0 individual pwm 1 high x x 0 1 gpwm1 1 high x x 1 0 gpwm2 1 high x x 1 1 100% on table 6. examples of settings for inselx[1:0] and pwmselx[1:0] resulting in outx states, which are independent from inx outxen inx inselx1 inselx0 pwmselx1 pwmselx0 state of outx x = 1, 2, 3, 5, 6 or 7 0x (1) 1. x: do not care. xx x x off 1 x 0 0 1 1 100% on 1 x 0 0 0 0 individual pwm 1x 0 1 0 1 gpwm1 1x 1 0 1 0 gpwm2 functional description L99CL01XP 16/60 docid023902 rev 4 pwm control modes in normal mode fo r outx, x = 4 or 8, if outenx = 1 out4 and out8 do not have any direct input or inselx[1:0] control bits. in normal mode, their behaviour is only determined by t he control registers pwmsel4[1:0] and pwmsel8[1:0], according to the following table: pulse skipping feature due to the output pulse shaping feature and th e thereof resulting propagation delay time of the smart switches, the duty cycle range close to 100% can not be generated by the device. therefore the pulse skipping feature (psf) is int egrated to generate this output duty cycle range in normal mode. the pulse skipping consists of fixed duty cycle patterns with 8 pwm cycles. when the corresponding psf bit [#1~#8:d8] is set, the pwm values 97.25%...99.61% (c3h?c7h) are generated individually for each channel by modulation of the duty cycle in discrete steps by the pulse skipping logic according to the following table: table 7. examples of settings for inselx[1:0] and pwmselx[1:0] resulting in outx states, which are dependent from inx. outxen inselx1 inselx0 pwmselx1 pwmselx0 state of outx x = 1, 2, 3, 5, 6 or 7 1 1 1 0 0 (individual pwm) and (inx) 1 1 1 0 1 (gpwm1) and (inx) 1 1 1 1 0 (gpwm2) and (inx) 1 1 1 1 1 according to inx table 8. pwm mode selection for out4 and out8 pwmselx1 pwmselx0 state of outx x=4 or 8 0 0 individual pwm 01 gpwm1 10 gpwm2 1 1 100% on table 9. duty cycle selection (psf enabled) duty cycle (%) hex (9bit) #1 #2 #3 #4 #5 #6 #7 #8 100.00% 0x100 256 256 256 256 256 256 256 256 99.61% 0x0ff 248 256 256 256 256 256 256 256 99.22% 0x0fe 248 256 256 256 248 256 256 256 98.82% 0x0fd 248 248 256 256 256 248 256 256 98.43% 0x0fc 248 248 256 256 248 248 256 256 98.04% 0x0fb 248 248 248 256 256 248 248 256 docid023902 rev 4 17/60 L99CL01XP functional description the psf is started with the next pwm cycl e after spi communication. the start step number can not be guaranteed. in reset condition psfx = [0], the pulse skipping feature is disabled. the psf is not available in fail mode. 2.7.3 overcurrent detection the over current shutdown threshold (i oc ) combined with the r dson can be programmed individually for each switch in two differ ent levels by spi command mode control [#9: d7~d0] (see section 3.1.5: control data registers (cdr) ): ? when ron bit is [0] the over current shutdown threshold is 1.5 a and the r dson is 600 m ? ? when ron bit is [1] the over current shutdown threshold is 750 ma and the r dson is 1 ? the setting of the ron bits can be monitore d by sdo register mode control [#9:d7~d0] (see section 3.1.6: status data registers ). in case of overcurrent failure the correspond ing outxen bit is automatically reset and the corresponding ocx status bit is set. this bi t is latched once an oc event is detected. to reset the diagnosis register, the condition has to be removed and an spi read and clear operation of the corresponding register has to be performed. 2.7.4 external resistor to achieve the precise internal slope control an d timings, an accurate external resistor is needed. the resistance has to be 12.4 k ? (1% tolerance) connected to gnd. if the resistor is removed or shorted, an rfai l failure is reported via spi [#1:d2] (see section 3.1.6: status data registers ). 2.7.5 channel voltage level comparator in addition to the digital diagnosis a mult iplexed channel out voltage comparator is implemented. the compared threshold is 5 v. the channel is selected via the muxen and the mux2:1 bits in the co ntrol data register [#0:d7:4]. the outl bit can be found in th e status data registers [#5,#6,#7,#8:d7]. 2.7.6 device protection a protection strategy enables light functiona lity even in case of failures inside the component of the light module. 97.65% 0x0fa 248 248 248 256 248 248 248 256 97,25% 0x0f9 248 248 248 248 248 248 248 256 table 9. duty cycle selection (psf enabled) (continued) duty cycle (%) hex (9bit) #1 #2 #3 #4 #5 #6 #7 #8 functional description L99CL01XP 18/60 docid023902 rev 4 therefore the component is protected against ? loss of any supply line ? loss of communication interface and pwmclk fail reverse polarity protection vs has an integrated ac tive reverse polarity protection. vsa, vsb, vsc and vsd have to be protected against reverse polarity by usi ng external protection devices (i.e. series diodes) in the battery supply lines. loss of supply lines the device is protected agai nst loss of any supply line. during loss of ? vs: the device can not drive any loads, and no communication via spi is possible. the device is in power down mode (refer to figure 4: state diagram ). when a valid vs voltage is applied again, the content of the r egisters are set to their default value. this event is reflected in the reset bit, at the first spi access. ? vsa, vsb, vsc or vsd: the device can not dr ive the correspondin g load group, but sends uvf_a / uvf_b / uvf_c or uvf_d flag via spi to the microcontroller. ? vdd: if the condition vdd < vddu v is present for more than t vdduv , the device enters in fail mode. the re freshing of the wd is disa bled as long as vdd < vdduv. all i/o lines have to be protected by external series resistors. loss of communication interface the following failures are consider ed as a loss of spi communication: loss of sck or csn, or csn is stuck to high or low. these failures are detected by the moni toring of the wd bit. in case of wd time-out, the device enters fail mode and the failure is reported by the status bit wdcerr (#1,bit 1). note: a short circuit of csn to low for a durati on exceeding csn time-out, additionally causes sdo to go in tri-state, in order to avoid a blocking of the whole spi bus. if sdi stuck to high of low, or if the number of sck cycles is not a multiple of 16, during a spi transaction, the device dire ctly enters fail mode. moreover the status register spif is set (#1, bit 5). logic input supervision the logic inputs are supervised by the device with different check strategies and consequential failures: table 10. error handling input/output signal check stra tegy system failure reaction pwm clock frequency too low no pwm feature a pwmclk fail is reported spi wd bit time-out fail mode spi sdi, sck, csn stuck at high or low fail mode spi sck fail fail mode docid023902 rev 4 19/60 L99CL01XP spi interface 3 spi interface a 16 bit spi interface (f max = 2 mhz) is used for control and diagnosis of the component. the spi offers daisy-chain-capability to prov ide high data rate, minimum circuit overheads and overall synchronization of multiple pwm modules. during each spi cycle a 16 bit word is transf erred into the control register of each device and a 16 bit word is received from each device. the data includes the toggling of a watchdog bi t, which indicates the proper operation of the spi interface. the watchdog bit has to be to ggled by every spi access starting after reset with ?0?. 3.1 spi communication 3.1.1 csn (chip sele ct (active low)) the csn terminal enables the spi communication with the microcontroller: ? the sdo output driver is enabled ? the device status data is latched to the outpu t shift registers on the falling edge of the csn ? the input shift register data is latched into the addressed registers on the rising edge of csn csn has an internal pull up resistor and a csn timeout is implemented. if csn is kept low for a duration, which is longer than t csn time-out, the incoming frame is considered as invalid and the sdo goes to tri-state. the csn ti me-out avoids that a sh ort circuit of csn to gnd blocks the spi bus. 3.1.2 sck (serial input clock) the sck terminal clocks the internal shift registers of the device. the sdi terminal accepts data into the input shift register on the falling edge of the sck signal, while the sdo terminal shifts output data to the sdo line driver on the rising edge of the sck signal (mcu setting: cpha = 1; cpol = 0). the sck terminal has to be in logic [0] state whenever csn makes any transition. when csn is logic [1] state, signals at the sck and sdi inputs are ignored and sdo driver output is in tri-state condition (high impedan ce). the L99CL01XP requires a number of sck cycles, which is a multiple of 16, during an spi transaction. if this condition is not met, the device enters fail mode. sck has an internal pull down resistor. 3.1.3 sdi (serial data input) the sdi pin is the data input terminal of the spi communication interface. the input has an internal pull down resistor. wr iting all [0] or all [1] to sdi within one spi frame will generate an spi fail (stuck @ error). spi interface L99CL01XP 20/60 docid023902 rev 4 the implemented spi requires a 16 bit stream of serial data, starting with d15 and ending with d0. 3.1.4 sdo (serial data output) the sdo pin is the data output terminal of the spi communication interface. the sdo terminal is in tri-stat e condition unless csn input is in logic [0] state. when csn is in logic [0] state, the data from the output shift registers is sent via the sdo pin. the sdo terminal changes the st ate at the rising edge of the sck input and reads out on the falling edge of sclk. 3.1.5 control data registers (cdr) the data sent to the device will be latched into the internal co ntrol registers with the rising edge of csn after a valid spi cycle is performed. the written data can be read back by sett ing the ramread bit d9 in the initialization register #0. after reset all registers ar e by default [0] (except sdoa0 is [1]). cdr base address = 0x00h the cdr register are shown in table 11: cdr registers table 11. cdr registers register address offset reset value initialization register 0x00h 0x0001h address #1-#8 chx control address #1 chx control 0x01h 0x1000h address #2 chx control 0x02h 0x2000h address #3 chx control 0x03h 0x3000h address #4 chx control 0x04h 0x4000h address #5 chx control 0x05h 0x5000h address #6 chx control 0x06h 0x6000h address #7 chx control 0x07h 0x7000h address #8 chx control 0x08h 0x8000h address #9 mode control 0x09h 0x9000h address #10 out enable 0x0ah 0xa001h address #11 pwmsel / insel ch1 + ch2 0x0bh 0xb000h address #12 pwmsel / insel ch3 + ch4 + ch5 0x0ch 0xc001h address #13 pwmsel / insel ch6 + ch7 + ch8 0x0dh 0xd000h address #14 global pwm1 0x0eh 0xe000h address #15 global pwm2 0x0fh 0xf000h docid023902 rev 4 21/60 L99CL01XP spi interface initialization register address: base address + 0x00h type: r, r/w reset: 0x0001h note: writing all [0] to th is register will generate a spi fail (stuck @ ?0?). 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 address wd no clear ram read pwmsync muxen mux2 mux1 mux0 soa3 soa2 soa1 soa0 r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15:12 address bit 11 wd: watchdog toggle bit (75ms, start with [0] after reset, toggled with every spi access) bit 10 noclear: with this bit set to: 0: every read access clears the read out status bits 1: any reported status from the read and clear flags are not cleared by a read the clear of the read and clear flags will be re-enabled by writing a [0] to this bit. bit 9 readram: with this bit set to: 0: the addressed status data register (see section 3.1.4: sdo (serial data output) ) is sent back via sdo 1: the addressed control data register is sent back via sdo. this is to verify the written data in the device. note: the read back of the status data registers will be re-enabled by writing a [0] to this bit. bit 8 pwmsync: internal pwm counter reset. writ ing a ?1? to this register will reset the internal pwm counter after valid spi command and csn hi gh. this bit is automatically reset after synchronization. bit 7 muxen: enable current sense output and the out voltage level comparator 0: cs pin disabled / out voltag e comparator disabled (default) 1: cs pin enable / out voltage comp arator enabled (see mux[2:0]) setting spi interface L99CL01XP 22/60 docid023902 rev 4 address #1-#8 chx control address: base address + 0x0yh (y = 0x01h to 0x08h) type: r, r/w reset: 0xy000h bit 6:4 mux[2:0]: binary decoded selection of curre nt sense output and the out voltage level comparator 000: channel 1 selected (default 001: channel 2 selected 010: channel 3 selected 011: channel 4 selected 100: channel 5 selected 101: channel 6 selected 110: channel 7 selected 111: channel 8 selected bit 3:0 sdoa[3:0]: address of next sdo data word (also see readram bit) 0000: readram = 0: address #1 selected, else address #0 0001: address #1 selected (default) 0010: address #2 selected 0011: address #3 selected 0100: address #4 selected 0101: address #5 selected 0110: address #6 selected 0111: address #7 selected 1000: address #8 selected 1001: address #9 selected 1010: address #10 selected 1011: address #11 selected 1100: address #12 selected 1101: address #13 selected 1110: address #14 selected 1111: address #15 selected 1514131211109876543210 address wd phx1 phx0 psfx ixdc7 ixdc6 ixdc5 ixdc4 ixdc3 ixdc2 ixdc1 ixdc0 r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15:12 address bit 11 wd: watchdog toggle bit (75ms, start with [0] after reset, toggled with every spi access) docid023902 rev 4 23/60 L99CL01XP spi interface address #9 mode control address: base address + 0x09h type: r, r/w reset: 0x9000h bit 10:9 phx[1:0]: binary decoded pwm phase shift selection (0, 90, 180, 270) 00: 0 phase (default) 01: 90 phase 10: 180 phase 11: 270 phase bit 8 psfx: pulse skipping enable 0: disabled 1: enabled bit 7:0 dcx7:0: channel individual duty cycl e programmable from 0x00 to 0xff dutycycle value in % dc[%] = value*100/256 0x00h: 0% 0x01h: 0.39% 0x02h: 0.78% .... 0xffh: 99.61% 1514131211109 8 7 6543210 address wd res 0 ocbln ron8 ron7 ron6 ron5 ron4 ron3 ron2 ron1 r r/w r r r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15:12 address bit 11 wd: watchdog toggle bit (75ms, start with [0] after reset, toggled with every spi access) bit 10 reserved bits have to be written with 0 bit 9 0 bit 8 ocbln: oc blanking disable 0: oc blanking = 150us blanking after outx on enabled (default) 1: oc blanking = 150us blanking after outx on disabled bit 7:0 ron8:1: defines over current threshold and r dson value 0: oc threshold = 1.5a and r dson = 600m ? (ol high threshold) (default) 1: oc threshold = 750ma and r dson = 1 ? (ol low threshold) spi interface L99CL01XP 24/60 docid023902 rev 4 address #10 out enable address: base address + 0x0ah type: r, r/w reset: 0xa001h address #11 pwmsel / insel ch1 + ch2 address: base address + 0x0bh type: r, r/w reset: 0xb000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 address wd res res res out8en out7en out6en out5en out4en out3en out2en out1en r r/w r r r r/w r/w r/w r/w r/w r/w r/w r/w bit 15:12 address bit 11 wd: watchdog toggle bit (75ms, start with [0] after reset, toggled with every spi access) bit 10:8 reserved bits have to be written with 0 bit 7:0 outen8:1: enables the output in normal mode. in case of ovx, uvx, tsdx or ocx the corresponding bits are cleared and therefore the outx is switched off. 0: disabled (default) 1: enabled (out corresponding inselx, pwmselx and inx) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 address wd res res res insel21 insel20 pwmsel21 pwmsel20 insel11 insel10 pwmsel11 pwmsel10 r r/w r r r r/w r/w r/w r/w r/w r/w r/w r/w bit 15:12 address bit 11 wd: watchdog toggle bit (75ms, start with [0] after reset, togg led with every spi access) bit 10:8 reserved bits have to be written with 0 bit 7:6 - bit 3:2 inselx[1:0]: inx func tion selector see section 2.7.2: pwm module bit 5:4 - bit 1:0 pwmselx[1:0]: pwm function selector see section 2.7.2: pwm module docid023902 rev 4 25/60 L99CL01XP spi interface address #12 pwmsel / insel ch3 + ch4 + ch5 address: base address + 0x0ch type: r, r/w reset: 0xc001h address #13 pwmsel / insel ch6 + ch7 + ch8 address: base address + 0x0dh type: r, r/w reset: 0xd000h 1514131211109876543210 address wd res insel51 insel50 pwmsel51 pwmsel50 pwmsel41 pwmsel40 insel31 insel30 pwmsel31 pwmsel30 r r/w r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15:12 address bit 11 wd: watchdog toggle bit (75ms, start with [0] after reset, toggled with every spi access) bit 10 reserved bits have to be written with 0 bit 9:8 - bit 3:2 inselx[1:0]: inx func tion selector see section 2.7.2: pwm module bit 7:4 - bit 1:0 pwmselx[1:0]: pwm function selector see section 2.7.2: pwm module 1514131211109876543210 address wd res pwmsel81 pwmsel80 insel71 insel70 pwmsel71 pwmsel70 insel61 insel60 pwmsel61 pwmsel60 r r/w r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15:12 address bit 11 wd: watchdog toggle bit (75ms, start with [0] after reset, togg led with every spi access) bit 10 reserved bits have to be written with 0 bit 7:6 - bit 3:2 see section 2.7.2: pwm module bit 5:4 - bit 1:0 see section 2.7.2: pwm module spi interface L99CL01XP 26/60 docid023902 rev 4 address #14 global pwm1 address: base address + 0x0eh type: r, r/w reset: 0xe000h address #15 global pwm2 note: writing all [1] to th is register will generate a spi fail (stuck @ ?1?). address: base address + 0x0fh type: r, r/w reset: 0xf000h 1514131211109876543210 address wd 0 0 0 g1dc7 g1dc6 g1dc5 g1dc4 g1dc3 g1dc2 g1dc1 g1dc0 r r/w r r r r/w r/w r/w r/w r/w r/w r/w r/w bit 15:12 address bit 11 watchdog toggle bit (75ms, start with [0] after reset, toggled with every spi access) bit 10:8 0 bit 7:0 g1dcx: global 1 duty cycle progra mmable from 0x00 to 0xff: dutycycle value in %; dc[%] = value * 100/256 0x00h: 0% 0x01h: 0.39% 0x02h: 0.78% .... 0xffh: 99.61% 1514131211109876543210 address wd 0 0 0 g2dc7 g2dc6 g2dc5 g2dc4 g2dc3 g2dc2 g2dc1 g2dc0 r r/w r r r r/w r/w r/w r/w r/w r/w r/w r/w docid023902 rev 4 27/60 L99CL01XP spi interface all sdi input data values, are latched into the registers at the rising edge of csn if the communication is valid (multiple of 16 scks and data consistency check). bit 15:12 address bit 11 wd: watchdog toggle bit (75ms, start with [0] after reset, toggled with every spi access) bit 10:8 0 bit 7:0 g2dcx: global 2 duty cycle programmable from 0x00 to 0xff dutycycle value in %; dc[%] = value * 100/256 0x00h: 0% 0x01h: 0.39% 0x02h: 0.78% .... 0xffh: 99.61% L99CL01XP spi interface docid023902 rev 4 28/60 table 12. control data register register address control data #d15d14d13d12d11d10 d9 d8d7d6d5 d4d3d2d1 d0 initialization 0 0 0 0 0 wd no clear ram read pwmsync muxen mux2 mux1 mux0 soa3 soa2 soa1 soa0 ch1 control 1 0 0 0 1 wd ph11 ph10 psf1 i1dc7 i1dc6 i1dc5 i1dc4 i1dc3 i1dc2 i1dc1 i1dc0 ch2 control 2 0 0 1 0 wd ph21 ph20 psf2 i2dc7 i2dc6 i2dc5 i2dc4 i2dc3 i2dc2 i2dc1 i2dc0 ch3 control 3 0 0 1 1 wd ph31 ph30 psf3 i3dc7 i3dc6 i3dc5 i3dc4 i3dc3 i3dc2 i3dc1 i3dc0 ch4 control 4 0 1 0 0 wd ph41 ph40 psf4 i4dc7 i4dc6 i4dc5 i4dc4 i4dc3 i4dc2 i4dc1 i4dc0 ch5 control 5 0 1 0 1 wd ph51 ph50 psf5 i5dc7 i5dc6 i5dc5 i5dc4 i5dc3 i5dc2 i5dc1 i5dc0 ch6 control 6 0 1 1 0 wd ph61 ph60 psf6 i6dc7 i6dc6 i6dc5 i6dc4 i6dc3 i6dc2 i6dc1 i6dc0 ch7 control 7 0 1 1 1 wd ph71 ph70 psf7 i7dc7 i7dc6 i7dc5 i7dc4 i7dc3 i7dc2 i7dc1 i7dc0 ch8 control 8 1 0 0 0 wd ph81 ph80 psf8 i8dc7 i8dc6 i8dc5 i8dc4 i8dc3 i8dc2 i8dc1 i8dc0 mode control 9 1 0 0 1 wd res 0 ocbln ron8 ron7 ron6 ron5 ron4 ron3 ron2 ron1 out enable 10 1 0 1 0 wd res res res out8en out7en out6en out5en out4en out3en out2en out1en pwmsel / insel ch1 + ch2 11 1 0 1 1 wd res res res insel21 insel20 pwmsel21 pwm sel20 insel11 insel10 pwmsel11 pwmsel10 pwmsel / insel ch3 + ch4 + ch5 12 1 1 0 0 wd res insel51 insel50 pwm sel51 pwm sel50 pwmsel41 pwmsel40 insel31 insel30 pwmsel31 pwmsel30 pwmsel / insel ch6 + ch7 + ch8 13 1 1 0 1 wd res pwmsel81 pwmsel80 insel71 insel70 pwmsel71 pwmsel70 insel61 insel60 pwmsel61 pwmsel60 global pwm1 14 1 1 1 0 wd 0 0 0 g1dc7 g1dc6 g1dc5 g1dc4 g1dc3 g1dc2 g1dc1 g1dc0 global pwm2 15 1 1 1 1 wd 0 0 0 g2dc7 g2dc6 g2dc5 g2dc4 g2dc3 g2dc2 g2dc1 g2dc0 docid023902 rev 4 29/60 L99CL01XP spi interface 3.1.6 status data registers by accessing the status registers, the read and clear flags are cleared after rising csn edge. all read and cl ear flags are latched and keep the status till re ad out. all other flags report the actual status and are therefore not clearable. by setting the noclear flag d10 in initialisation register #0, this automatic clear is prohibited. if a flag is set during read out phase the fl ag is latched and will be reported with the next read. the spi output delivers the data set programmed by the bits d9 (readram option) and d3:0 (sdoa3:0) inside the control data register [#0] of the spi: sdr base address = 0x00h the sdr register are shown in table 13: sdr registers address #0 a read access to status register #0 is not allowe d. it is interpreted as sdo is shorted to "0" and lead the device to enter fail mode address #1 device status 1 table 13. sdr registers register address offset reset value address #0 0x00h 0x00h address #1 device status 1 0x01h 0x00h address #2 device status 2 0x02h 0x00h address #3 device status 3 0x03h 0x00h address #4 quick status 0x04h 0x00h address #5-#8 status chx+chy address #5 status ch1+ch2 0x05h 0x00h address #6 status ch31+ch4 0x06h 0x00h address #7 status ch5+ch6 0x07h 0x00h address #8 status ch7+ch8 0x08h 0x00h address #9 mode control 0x09h 0x00h address #10 out enable 0x0ah 0x00h address #11 inx status 0x0bh 0x00h address #12 silicon version 0x0ch 0x01h 1514131211109876543210 address failsafe svf x (1) 1. x: do not care dsf chip reset vddf spif limp pclkf rfail wdc err wdc0 r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w spi interface L99CL01XP 30/60 docid023902 rev 4 address: base address + 0x01h type: r, r/w reset: 0x00h bit 15:12 address bit 11 failsafe: 0: device is in normal mode 1: device is in fail mode (directdrive enabled) bit 10 svf: logical or combination of all ov, uv, ovx, uvx 0: supply voltage in operating range 1: supply voltage failure bit 9 x: do not care bit 8 dsf: logical or combination of vddf or spif or limp or pclkf or rfail or wdcerr 0: no fail detected 1: fail detected bit 7 chip reset: indicates if all r egisters are previously reset, cleared with the first spi read (by default #1) 0: device has not been previously reset 1: all registers are in reset state (clear ed with first valid spi command after reset) bit 6 vddf: vdd fail occurred 0: no vdd fail detected 1: vdd fail detected bit 5 spif: spi clock fail or sdi stuck @ detected 0: no spi fail detected 1: spi fail detected (spi cloc k cycles during a transaction is not a multiple of 16, stuck @ 0 or 1 at sdi detected) bit 4 limp: limp pin high detected 0: no limp high detected 1: limp high detected bit 3 pclkf: pwmclk fail detected 0: no pwmclk fail detected 1: pwmclk fail detected bit 2 rfail: external r failure detected 0: r external connected correctly 1: r external fail detected bit 1 wdcerr: wdc time-out or wd toggle bit fail detected 0: no watchdog failure 1: watchdog fail detected bit 0 wdc0: wdc 50% flag 0: watchdog 50% time-out not reached 1: watchdog 50% time-out reached docid023902 rev 4 31/60 L99CL01XP spi interface address #2 device status 2 address: base address + 0x02h type: r, r/w reset: 0x00h address #3 device status 3 1514131211109876543210 address failsafe svf x (1) 1. x: do not care dsf0000tsdtwovfuvf r r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15:12 address bit 11 failsafe: 0: device is in normal mode 1: device is in fail mode (directdrive enabled) bit 10 svf: logical or combination of all ov, uv, ovx, uvx 0: supply voltage in operating range 1: supply voltage failure bit 9 x: do not care bit 8 dsf: logical or combination of vddf or spif or limp or pclkf or rfail or wdcerr 0: no fail detected 1: fail detected bit 7:4 0 bit 2 tw: logical or combination of all twx 0: no thermal warning detected 1: thermal warning detected bit 1 ovf: overvoltage at vs detected 0: no over voltage detected 1: over voltage detected (ovf is latch ed once an overvoltage on vs is detected) bit 0 uvf: undervoltage at vs detected 0: no under voltage detected 1: under voltage detected (uvf is latc hed once an undervoltage on vs is detected) 1514131211109876543210 address failsafe svf x (1) 1. x: do not care dsf ovf_a uvf_a ovf_b uvf_b ovf_c uvf_c ovf_d uvf_d r r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w r/w spi interface L99CL01XP 32/60 docid023902 rev 4 address: base address + 0x03h type: r, r/w reset: 0x00h bit 15:12 address bit 11 failsafe: 0: device is in normal mode 1: device is in fail mode (directdrive enabled) bit 10 svf: logical or combination of all ovx, uvx 0: supply voltage in operating range 1: supply voltage failure bit 9 x: do not care bit 8 dsf: logical or combination of vddf or spif or limp or pclkf or rfail or wdcerr 0: no fail detected 1: fail detected bit 7 ovf_a (1) : overvoltage at vsa detected 0: no over voltage detected 1: over voltage detected, out1en and ou t2en are cleared automatically (channel off) bit 6 uvf_a (1) : undervoltage at vsa detected 0: no under voltage detected 1: under voltage detected, out1en and out2en are cleared automatically (channel off) bit 5 ovf_b (1) : overvoltage at vsb detected 0: no over voltage detected 1: over voltage detected, out3en and ou t4en are cleared automatically (channel off) bit 4 uvf_b (1) : undervoltage at vsb detected 0: no under voltage detected 1: under voltage detected, out3en and out4en are cleared automatically (channel off) bit 3 ovf_c (1) : overvoltage at vsc detected 0: no over voltage detected 1: over voltage detected, out5en and ou t6en are cleared automatically (channel off) docid023902 rev 4 33/60 L99CL01XP spi interface address #4 quick status address: base address + 0x04h type: r, r/w reset: 0x00h bit 2 uvf_c (1) : undervoltage at vsc detected 0: no under voltage detected 1: under voltage detected, out5en and out6en are cleared automatically (channel off) bit 1 ovf_d (1) : overvoltage at vsd detected 0: no over voltage detected 1: over voltage detected, out7en and ou t8en are cleared automatically (channel off) bit 0 uvf_d (1) : undervoltage at vsd detected 0: no under voltage detected 1: under voltage detected, out7en and out8en are cleared automatically (channel off) 1. ovf_x and uvf_x are latched, once an overvoltage, respectively, and undervoltage is detected on vs_x. 1514131211109876543210 address failsafe svf x (1) 1. x: do not care dsf qsf8 qsf7 qsf6 qsf5 qsf4 qsf3 qsf2 qsf1 r r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15:12 address bit 11 failsafe: 0: device is in normal mode 1: device is in fail mode (directdrive enabled) bit 10 svf: logical or combination of all ovx, uvx 0: supply voltage in operating range 1: supply voltage failure bit 9 x: do not care bit 8 dsf: logical or combination of vddf or spif or limp or pclkf or rfail or wdcerr 0: no fail detected 1: fail detected bit 7:0 qsfx[7:0]: channel specific logical or combination of tsdx or twx_th2 or twx_th1 or ocx or olx 0: no fail detected 1: fail detected spi interface L99CL01XP 34/60 docid023902 rev 4 address #5-#8 status chx+chy address: base address + 0x0yh (y = 0x05 to 0x08h) type: r, r/w reset: 0x00h 1514131211109876543210 address failsafe svf x (1) 1. x: do not care dsf outl tsdxy twxyth2 twxyth1 ocy x (1) ocx x (1) r r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15:12 address bit 11 failsafe: 0: device is in normal mode 1: device is in fail mode (directdrive enabled) bit 10 svf: logical or combination of all ovx, uvx 0: supply voltage in operating range 1: supply voltage failure bit 9 x: do not care bit 8 dsf: logical or combination of vddf or spif or limp or pclkf or rfail or wdcerr 0: no fail detected 1: fail detected bit 7 outl: logical read back value of selected [#0:d7~d4] outx channel. this information can be used to distinguish between open load and short to vsx in off state. 0: outx is low 1: outx is high bit 6 tsdxy: thermal shutdown flag of channel x or y 0: no thermal shutdown detected 1: thermal shutdown detected, the corres ponding outxen are cleared automatically (channel off). tsdxy is latched off once an thermal shutdown occured. bit 5 twxy_th2: thermal warning threshold2 flag of channel x or y 0: no thermal warning detected 1: thermal warning detected. th is bit is not latched. on ce the temperature on outputs x/y is below tjtw2, this status bit is reset. bit 4 twxy_th1: thermal warning threshold1 flag of channel x or y 0: no thermal warning detected 1: thermal warning detected bit 3, 1 ocx/y: channel specific over current flag 1: overcurrent detected, the corresponding outxen is cleared automatically (channel off) bit 2, 0 x: do not care docid023902 rev 4 35/60 L99CL01XP spi interface address #9 mode control address: base address + 0x09h type: r, r/w reset: 0x00h address #10 out enable 1514131211109876543210 address failsafe svf x (1) 1. x: do not care dsf ron8 ron7 ron6 ron5 ron4 ron3 ron2 ron1 r r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15:12 address bit 11 failsafe: 0: device is in normal mode 1: device is in fail mode (directdrive enabled) bit 10 svf: logical or combination of all ovx, uvx 0: supply voltage in operating range 1: supply voltage failure bit 9 x: do not care bit 8 dsf: logical or combination of vddf or spif or limp or pclkf or rfail or wdcerr 0: no fail detected 1: fail detected bit 7:0 ron8:1: copy of over current threshold and r dson value defined in input register #9 0: oc threshold = 1.5a and r dson = 500m ? (ol high threshold) 1: oc threshold = 750ma and r dson = 1 ? (ol low threshold) 1514131211109876543210 address failsafe svf x (1) 1. x: do not care dsf out8en out7en out6en out5en out4en out3en out2en out1en r r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w r/w spi interface L99CL01XP 36/60 docid023902 rev 4 address: base address + 0x0ah type: r, r/w reset: 0x00h address #11 inx status address: base address + 0x0bh type: r, r/w reset: 0x00h bit 15:12 address bit 11 failsafe: 0: device is in normal mode 1: device is in fail mode (directdrive enabled) bit 10 svf: logical or combination of all ovx, uvx 0: supply voltage in operating range 1: supply voltage failure bit 9 x: do not care bit 8 dsf: logical or combination of vddf or spif or limp or pclkf or rfail or wdcerr 0: no fail detected 1: fail detected bit 7:0 outen8:1: copy of output enable in normal mode status defined in input register #10 0: disabled 1: enabled (out corresponding inselx and pwmselx) 1514131211109876543210 address failsafe svf x (1) 1. x: do not care dsf 0 in7 in6 in5 0 in3 in2 in1 r r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w r/w bit 15:12 address bit 11 failsafe: 0: device is in normal mode 1: device is in fail mode (directdrive enabled) bit 10 svf: logical or combination of all ovx, uvx 0: supply voltage in operating range 1: supply voltage failure bit 9 x: do not care docid023902 rev 4 37/60 L99CL01XP spi interface bit 8 dsf: logical or combination of vddf or spif or limp or pclkf or rfail or wdcerr 0: no fail detected 1: fail detected bit 7:4 - bit 2:0 in7, in6, in5, in3, in2, in1: corresponding inx pin value 0: input logical [0] detected 1: input logical [1] detected bit 3 0 spi interface L99CL01XP 38/60 docid023902 rev 4 address #12 silicon version address: base address + 0x0ch type: r, r/w reset: 0x01h 1514131211109876543210 address failsafe svf x (1) 1. x: do not care dsf0000sv3sv2sv1sv0 r r/w r/w r r/w r r r r r/w r/w r/w r/w bit 15:12 address bit 11 failsafe: 0: device is in normal mode 1: device is in fail mode (directdrive enabled) bit 10 svf: logical or combination of all ovx, uvx 0: supply voltage in operating range 1: supply voltage failure bit 9 x: do not care bit 8 dsf: logical or combination of vddf or spif or limp or pclkf or rfail or wdcerr 0: no fail detected 1: fail detected bit 7:4 0 bit 3:0 sv3:0: binary coded version of silicon 0001: silicon version spi interface L99CL01XP 39/60 docid023902 rev 4 table 14. status data register (1) register address control data # d1 5 d1 4 d1 3 d1 2 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 na 0 0 0 0 0 x (2) xxxxxxxxxxx device status 1 1 0 0 0 1 fail safe svf x dsf chip reset vddf spif limp pclkf rfail wdc err wdc0 device status 2 2 0 0 1 0 fail safe svf x dsf 0 0 0 0 tsd tw ovf uvf device status 3 3 0 0 1 1 fail safe svf x dsf ovf_a uvf_a ovf_b uvf_b ovf_c uvf_c ovf_d uvf_d quick status40100fail safesvfxdsfxxxxxxxx diag ch1 + 2 5 0 1 0 1 fail safe svf x dsf outl tsd12 tw12th2 tw12th1 oc2 x oc1 x diag ch3 + 4 6 0 1 1 0 fail safe svf x dsf outl tsd34 tw34th2 tw34th1 oc4 x oc3 x diag ch5 +6 7 0 1 1 1 fail safe svf x dsf outl tsd56 tw56th2 tw56th1 oc6 x oc5 x diag ch7 + 8 8 1 0 0 0 fail safe svf x dsf outl tsd78 tw78th2 tw78th1 oc8 x oc7 x mode control 9 1 0 0 1 fail safe svf x dsf ron8 ron7 ron6 ron5 ron4 ron3 ron2 ron1 out enable 1 0 1 0 1 0 fail safe svf x dsf out8en out7en out6en out5en out4en out3en out2en out1en inx status 1 1 1 0 1 1 fail safe svf x dsf 0 in7 in6 in5 in4 in3 in2 in1 silicon version 1 2 1 1 0 0 fail safe svf x dsf 0 0 0 0 sv3 sv2 sv1 sv0 1. grey cells: read and clear flags. 2. x: do not care. spi interface L99CL01XP 40/60 docid023902 rev 4 3.2 operating modes 3.2.1 standby mode the standby mode is the default mode of the device after power on (vs > vs uv ) without applying any wake up signals (high signal on one of the inx pins or on en pin). during standby mode ? the current consumption of the de vice is minimized (vdd, vs, vsx) ? the internal circuitry is deactivated ? all outputs are off and protected against mistreatment 3.2.2 wake up and operating modes the device leaves the standby mode if one of the following wake-up events occurs. refer to figure 4 : figure 4. state diagram 3 r z h u ' r z q 2 x w s x w v w d j h v d u h 2 ) ) 1 r u p d o 0 r g h 2 x w s x w v w d j h v d f f r u g l q j w r , 1 [ d q g 6 3 , v h w w l q j v ' l d j q r v w l f w k u r x j k & 6 d y d l o d e o h 6 3 , d f w l y h 6 3 , ' l d j q r v w l f d y d l o d e o h ) d l o 0 r g h 2 x w s x w v w d j h v d f f r u g l q j w r , q [ 6 3 , d f w l y h 6 3 , ' l d j q r v w l f d y d l o d e o h ' l d j q r v w l f w k u r x j k & 6 d y d l o d e o h 5 2 1 v h w w r / r z 2 & e o d q n w l p h d f w l y d w h g 6 w d q g e \ 0 r g h 2 x w s x w v w d j h v d u h 2 ) ) / r z f r q v x p s w l r q i u r p 9 6 9 6 [ 9 ' ' 6 3 , l q d f w l y h 9 6 ! 9 6 8 9 ( 1 + l j k 2 u , 1 [ + l j k 2 u , 1 [ w l p h u u x q q l q j ( 1 / r z d q g , 1 [ / r z d q g , 1 [ w l p h u q r w u x q q l q j 2 q h r i w k h h y h q w r f f x u : ' i d l o x u h 2 u / , 0 3 + l j k 2 5 6 ' , v w x f n ? r u ? 3 [ ) ) r u [ 2 5 z u r q j 6 & / . f o r f n f \ f o h v l v q r w d p x o w l s o h r i 2 5 9 ' ' ) d l o 2 5 ( 1 / r z z k l o h r q h r i w k h , 1 [ l v + l j k i r u d g x u d w l r q h [ f h h g l q j : ' 7 l p h r x w 5 h d g & o h d u r i ' h y l f h 6 w d w x v 5 h j i r o o r z h g e \ : ' e l w w r j j o h g f r q v h f x w l y h 6 3 , z l w k : ' d q g : ' 5 h v h w w u d q v l w l r q 6 3 , u h j l v w h u f r q w u r o u h j u h v h w w r g h i d x o w y d o x h v 6 w d w x v u h j u h v h w & r u u h f w : ' u h i u h v k 9 6 9 6 8 9 ( 1 / r z d q g , 1 [ / r z d q g , 1 [ w l p h u l v q r w u x q q l q j ? v 1 r w h l i ( 1 / r z l w l v q r w s r v v l e o h w r h [ l w i u r p ) d l o 0 r g h w r 1 r u p d o p r g h g h v s l w h w k l v v h t x h q f h ( " 1 ( $ ' 5 docid023902 rev 4 41/60 L99CL01XP spi interface wakeup sources are as follows: ? enable ? input signals in1, in2, in3, in5, in6, in7 ? toggle signal: this signal is an or combinat ion from all input signals by a retriggerable mono stable. it keeps the device active for a dedicated time (t toggle ) after the last negative edge at any input signal in1, in2, in3, in5, in6, in7: figure 5. toggle signal when enable is off but another wakeup source is still acti ve this can be monitored by the pwmclk(wake) pin which is an acti ve high output during pending wake. by leaving the failmode a ll internal registers will be reset to default state. 3.2.3 cold start ? power up reset the cold start sequence describes the power up and the startup of the device. when vs is in the specified ranges and the inx or the enable pin are on a logical [0] level the device is in standby. when inx or enable change their le vels to logical [1] the internal en for the power on reset circuit (por) and the oscillato r (osc) will be set to [1] and the two blocks will be enabled. the device is star ted. the internal por is re leased and the oscillator is running. the internal registers are reset. to their default value and the device enter normal mode 3.2.4 normal mode the device enters normal mode: ? either from standby mode if vdd > vdduv, limp =low, and en goes from low to high. refer to section 3.2.3: cold st art ? power up reset ? or from fail mode, refer to section 3.2.6: warm start ? (t ransition from failmode to normal over internal reset) in normal mode, the spi is active and the ou tput stages are controlled by the spi and the inx settings. the spi diagnostics and the cu rrentsense pin are both available. the protections are fully functional. normal mode is left with the following conditions: ? vdd falls below vdduv ? a watchdog failure occurs: wrong toggling of wd bit or no toggling of the wd bit for a duration exceeding twd ? en goes low ? an spi failure occurs ? limp goes to low t_ t oggle in1 or in2 or in3 or in5 or in 6 or in7 toggle spi interface L99CL01XP 42/60 docid023902 rev 4 3.2.5 fail mode the L99CL01XP offers th e possibility to control out1-3 a nd out5-7 in case of fail safe event by the corresponding inx pins (refer to table 15 ) the fail mode is activated if one of the conditions listed in the following table occurs. the operation in fail mode is reported by the status bit fail safe (any status register, bit11) and by one of the status bits: vdduv, spif, wd cerr, limp, depending on the cause of the activation of the fail mode. in this mode, the device?s spi is ac tive unless a vdd undervoltage occurs. the control registers behaves as described in the table 17 . the content of the status registers are kept during the transition to fail mode. table 15. mapping between the input pins and the outputs in fail mode pin corresponding output in1 out1 in2 out2 in3 out3 in5 out5 in6 out6 in7 out7 table 16. events leading to fail mode event related status bit delay to fail mode vdd undervoltage vdduv after t vdd_uv spi failure spif immediate watchdog check error wdcerr after wdtimeout limp = high limp after t limp during active mode, en goes from high to low while one of the inx ,x= 1-3, 5-6 is high (1) 1. when this condition occurs, the dev ice prevents the refresh of the wd toggle bit, leading to a watchdog timeout failure. as long as en = low, the refresh of the wd is blocked and the device cannot go to normal mode. wdcerr after wdtimeout table 17. control registers in fail mode control registers content during transition to fail mode write protection valid content initialization, #0 as before fail mode no yes chx control, #1-8 as before fail mode no no (1) mode control, #9 reset to default value yes (2) yes out enable, #10 as before fail mode no no (2) docid023902 rev 4 43/60 L99CL01XP spi interface the current sense is active and the kfactor is the one, which corresponds to the low ron setting. auto restart feature the auto restart feature is used to control the smart switches in case of overcurrent, under or over voltage failure conditions to provide a high availability of the outputs even when no supervising inte lligence of the microcontrolle r is available (fail mode). auto restart is enabled in case of ? overcurrent condition (ocx) of the corresponding channel ? under or over voltage condition (uvx or ovx) on the corresponding supply line in case of oc, uv or ov the corresponding outp ut or outputs are deactivated. in case of oc failure the output returns to fail mode direct drive after a dedicated time (t autorestart = 100 ms). during this on phase the diagnosis is restarted. when the failure is still present and the channel is tu rned off again. therefor e the output stays in this cyclic loop as long as the failure is present. in case of uv or ov the diagnosis is continuously running. after removing the failure condition (uv or ov) the switch returns to fail mode direct drive after a dedicated time within t autorestart . in case of over temperature shutdown (ots) t he switch enters ?latch off? state which can only be removed by a mode change to ?normal mode? or ?standby? (see chapter 3.2: operating modes ). pwmen/insel, #11-13 as before fail mode no no (2) global pwmx, #1-2 as before fail mode no no (2) 1. the pwm unit is disabled and the state of outx is according to the corresponding inx,x=1-3,5-7 regardless to the content of these registers. out4 and out8 are off. 2. while entering the fail mode, the content of the mode control register is reset to its default value and the device behaves accordingly: the rdson of the output is set to the low value and the overcurrent blank time is enabled. this control register is write-protected in fail mode. table 17. control registers in fail mode control registers content during transition to fail mode write protection valid content spi interface L99CL01XP 44/60 docid023902 rev 4 figure 6. fail mode status diagram 3.2.6 warm start ? (transition from fail mode to normal over internal reset) due to a possible unknown state of the internal registers a reset of the device is necessary by leaving fail mode. therefore a reset is generated when the device leaves fail mode with two consecutive valid spi commands with wd ?0? and wd ?1?. this is only possible when enable is logical [1] and the failure is removed (read and clear) before the two consecutive spi commands are sent. this kind of reset has no impact on the por and the osc. figure 7. reset mode ' l u h f w ' u l y h 2 8 7 [ , 1 [ $ x w r u h v w d u w 2 8 7 [ 2 ) ) / d w f k 2 i i 2 8 7 [ 2 ) ) , 1 [ k l j k $ 1 ' 2 & 8 9 [ r u 2 9 [ , 1 [ k l j k $ 1 ' 2 7 6 8 9 r u 2 9 u e f m b z u b v u p s f t u b s u b g u f s 0 $ u e f m b z n v m u j q m f p g u b v u p s f t u b s u " g u f s u i f s f n p w b m p g u i f 6 7 y p s 0 7 y d p o e j u j p o t ( " 1 ( $ ' 5 6 3 , 6 3 , : ' u h d g d q g f o h d u ) d l o : ' 1 r ) $ , / 5 ( 6 ( 7 6 3 , 6 3 , : ' 1 r ) $ , / : ' 1 r ) $ , / 6 3 , : ' ; u h d g d q g f o h d u ) d l o 5 ( 6 ( 7 2 s w l r q 2 s w l r q ( " 1 ( $ ' 5 docid023902 rev 4 45/60 L99CL01XP electrical specifications 4 electrical specifications 4.1 absolute maximum rating stressing the device ab ove the rating listed in table 18 may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other condition above those indicated in the operating se ctions of this specific ation is not implied. exposure to absolute maximum rating conditi ons for extended periods may affect device reliability. table 18. absolute maximum rating symbol parameter test condition value unit vsa, vsb, vsc, vsd supply voltage range for channel couples a, b, c and d short circuit; single pulse; t j = 25c (1) 6 to 24 v short circuit; repetitive pulse; -40c < t j <150c (1) 6 to 20 v load dump (400 ms) 40 v vs rev reverse polarity voltage range (2) -24 v v io logic input voltage range -0.3 to v dd +0.3 v i in clamp input clamping current maximum value of each pin 5 ma v out output voltage range -1.5 to v s +0.3 v v clamp_high outx, inx, limp, csn, enable, vs, vsa, vsb, vsc, vsd 42 v v clamp_low sdo, sdi, sck, pwmclk, cs, vdd, rext 7v t j junction operating temperature -40 to 150 c t stg storage temperature -55 to 150 c v esd electrostatic discharge (human body model, 100pf/1,5k) vs (3) , gnd, out1 ~ out8 4 kv all other pins 2 kv charge device model (cdm-aec- q100-011) 1000 v 1. also valid for vsa, vsb, vsc, vsd < 6 v 2. valid for vs. 3. valid for vsa, vsb, vsc, vsd. electrical specifications L99CL01XP 46/60 docid023902 rev 4 4.2 thermal data table 19. temperature warning and thermal shutdown symbol parameter min. typ. max. unit t jtw1 (1) 1. parameter guaranteed by design and characteri zation; not subject to production test. temperature warning threshold junction temperature 125 165 c t jtw2 (1) temperature warning threshold junction temperature 135 175 c t jtsd (1) thermal shutdown threshold junction temperature 155 195 c table 20. thermal data symbol parameter t yp. value unit r thj-amb thermal resistance junction-ambient (jedec jesd 51-5) (1)(2) 1. device mounted on two-layers 2s0p pcb with 2 cm 2 heatsink copper trace 2. one channel on. 48.5 c/w r thj-amb thermal resistance junction-ambient (jedec jesd 51-7) (2)(3) 3. device mounted on four-layers 2s2p pcb 19.5 c/w table 21. digital timings symbol parameter m in. typ. max. unit f int internal oscillator clock frequency 1.75 2 2.25 mhz t tsd (1) 1. parameter guaranteed by design and characteri zation; not subject to production test. internal twx and tsd filter time 20 25 30 s t vdd_uv (1) vdd uv detection time 20 25 30 s t vs_ov/uv (1) vs uv/ov detection time 20 25 30 s t limp (1) limp mode settling time 0.9 1.15 1.4 ms t rextf (1) r extern fail deglitch time 20 25 30 s t toggle (1) input toggle time 1.65 2.1 2.55 s t autorestart (1) auto restart delay time 100 130 160 ms t wd (1) watchdog timeout 60 75 90 ms t oc (1) overcurrent shutdown delay time 40 50 60 s t ocblank (1) oc blanking time 160 200 240 s t csn timeout (1) csn timeout 100 130 160 ms docid023902 rev 4 47/60 L99CL01XP electrical specifications 4.3 electrical characteristics v s = 6 v to 24 v, v dd = 4.5 v to 5.5 v, t j = -40c to 150c, unless otherwise specified. the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. table 22. electrical charact eristics (logic + inputs) symbol parameter test condition min. typ. max. unit vdd digital i/o supply voltage range 3.0 5.5 v vdd uv digital i/o supply undervoltage threshold at t j = 25c 2.0 2.5 3.0 v vdd uvhyst digital i/o supply undervoltage threshold hysteresis at t j = 25c 0.4 v i dd supply current in on-state from v dd 500 a i qdd standby current consumption from v dd at t j = 25c 5a vs uv battery supply under voltage flag at t j = 25c (1) 5.0 5.5 6.0 v vs uvhyst battery supply undervoltage flag hysteresis at t j = 25c 0.4 v vs ov battery supply overvoltage flag 30 32 34 v vs ovhyst battery supply overvoltage flag hysteresis 11.52v i s supply current in on-state from v s at v s =12v i outx =0a 10 ma i qs standby current consumption from v s at t j = 25c, v s =12v 5a v vddh logic input high level (2) all digital inputs connected to v dd 0.56 v dd 0.66 v dd 0.76 v dd v logic input high level (3) all digital inputs connected to v dd 0.52 v dd 0.58 v dd 0.64 v dd v v vddhyst input hysteresis (4) all digital inputs connected to v dd 0.16 v dd 0.22 v dd 0.26 v dd v v inth logic input high level (5) all digital inputs connected to internal 5v 1.4 1.7 2.0 v v inthyst logic input hysteresis (5) all digital inputs connected to internal 5v 0.4 0.6 0.8 v i l(off) off-state output current at v s =v sx =12v channel off; v out =0v 1a v ol output low voltage (6) i out = 5ma 0.5 v v oh output high voltage (6) i out = -5ma v dd ? 1.3 v electrical specifications L99CL01XP 48/60 docid023902 rev 4 v porh power on reset high threshold for v s at v dd = 5v 22.84v v porl power on reset high threshold for v s at v dd = 5v 22.94v r up (3) pull up resistor for logic pin 9 20 44 k ? r down (7) pull down resistor for logic pin 36 100 250 k ? f pwm pwm frequency range 100 400 hz f clk clock input frequency range 25.6 102.4 khz ? pwm pwm duty cycle re solution 1/256 % r ext external resistor range for rext pin 10 12.4 15 k ? r failh 15 k ? r faill 10 k ? v rext rext output voltage i out = 200 a 2.4 2.5 2.6 v f clk fail low (8) clock frequency fail detection range low frequency 10 khz 1. valid for vs, vsa, vsb, vsc, vsd. 2. valid for enable, sdi, sck, pwmclk 3. valid for csn 4. valid for enable, sdi, sck, pwmclk, csn. 5. valid for in1, in2, in3, in5, in6, in7, limp 6. valid for sdo 7. valid for enable, sdi, sck, inx, pwmclk, limp. 8. parameter guaranteed by design and characteri zation; not subject to production test. table 23. dynamic characteristics (spi) symbol parameter test condition min. typ. max. unit spi clk (1) spi clock frequency 2 mhz t csnqv (1) csn falling until sdo valid c out = 100pf 120 ns t csnqt (1) csn rising until sdo tristate c out = 100pf 4 s t sckqv (1) sck rising until sdo valid c out = 100pf 20 ns t scsn (1) csn setup time before sck rising 20 ns t ssdi (1) sdi setup time before sck falling 20 ns t hsck (1) minimum sck high time 125 ns t lsck (1) minimum sck low time 125 ns t hcsn (1) minimum csn high time 5 s t ssck (1) sck setup time before csn rising 50 ns table 22. electrical characterist ics (logic + inputs) (continued) symbol parameter test condition min. typ. max. unit docid023902 rev 4 49/60 L99CL01XP electrical specifications figure 8. spi timing 1. parameter guaranteed by design and characteri zation; not subject to production test. table 24. switching (v s =12v; t j =25c) symbol parameter test cond itions min. typ. max. unit t d(on) turn-on delay time r on [x] = 0 r load =32 ? ?25s t d(on) turn-on delay time r on [x] = 1 r load =16 ? ?25s t d(off) turn-off delay time r on [x] = 0 r load =32 ? ?25s t d(off) turn-off delay time r on [x] = 1 r load =16 ? ?25s (dv out /dt) on turn-on voltage slope ? 0.14 v/s (dv out /dt) off turn-off voltage slope ? 0.32 v/s t skew differential pulse skew ? -200 s csn sdo data out t csnqt t sckqv sck data out t lsck t hsck t scsn t hcsn data in data in t ssdi sdi t csnqv t ssck table 25. electrical charac teristics (out1 - out8) symbol parameter test condition min. typ. max. unit r dson output resistance ronx = [1]; i = 800 ma 0.35 0.6 1 ? ronx = [0]; i = 400 ma 0.65 1 1.7 ? i oc overcurrent shutdown threshold oc high range; on state (1) 1.2 1.5 1.8 a oc low range; on state (1) 0.6 0.75 0.9 a v outl selected outx voltage threshold 4.5 5 5.5 v electrical specifications L99CL01XP 50/60 docid023902 rev 4 i sense0 analog sense i out =0a; v cs =0v; channels in off-state; current sense multiplexer enabled on one of the outputs 0.5 a i out =0a; v cs =0v; channels in on-state; current sense multiplexer disabled 0.5 a t dsense1h current sense settling time from rising edge of cs pin maximum value for setting to 90% 5130250s k 1 current sense ratio at different currents i out /i cs ; ron[x] = 0; i out =50ma 450 1450 3500 i out /i cs ; ron[x] = 1; i out =30ma 300 725 1500 dk 1 /k 1 (2) current sense ratio drift with temperature i out /i cs ; ron[x] = 0; i out =50ma -40 40 % i out /i cs ; ron[x] = 1; i out =30ma -35 35 % k 2 current sense ratio at different currents i out /i cs ; ron[x] = 0; i out = 100 ma 1000 1650 2500 i out /i cs ; ron[x] = 1; i out =50ma 500 825 1250 dk 2 /k 2 (2) current sense ratio drift with temperature i out /i cs ; ron[x] = 0; i out = 100 ma -25 25 % i out /i cs ; ron[x] = 1; i out =50ma -25 25 % k 3 current sense ratio at different currents i out /i cs ; ron[x] = 0; i out = 300 ma 1500 1900 2200 i out /i cs ; ron[x] = 1; i out = 100 ma 650 900 1100 dk 3 /k 3 (2) current sense ratio drift with temperature i out /i cs ; ron[x] = 0; i out = 300 ma -10 10 % i out /i cs ; ron[x] = 1; i out = 100 ma -15 15 % k 4 current sense ratio at different currents i out /i cs ; ron[x] = 0; i out = 800 ma 1800 2000 2200 i out /i cs ; ron[x] = 1; i out = 400 ma 900 1000 1100 dk 4 /k 4 (2) current sense ratio drift with temperature i out /i cs ; ron[x] = 0; i out = 800 ma -7.5 7.5 % i out /i cs ; ron[x] = 1; i out = 400 ma -7.5 7.5 % table 25. electrical characteristics (out1 - out8) (continued) symbol parameter test condition min. typ. max. unit docid023902 rev 4 51/60 L99CL01XP electrical specifications i cs_offset i cs offset current @25c i cs @ i out =0a 0 9 25 a i cs_drift_ratio (2) i cs_offset variation between i cs at 25c and i cs at 150c or i cs at -40c -60 60 % ? k lron offset compensated k-factor at low r on i out = 50 ma 1725 2090 ? k hron offset compensated k-factor at high r on i out = 30 ma 850 1040 i cs_max current sense full scale range typical value for oc at 25c 850 a v cs current sense output voltage nominal voltage range 0 v dd - 1 v 1. value can be higher and vary during active pulse shaping 2. parameter guaranteed by design and characteri zation; not subject to production test. table 26. electrical transient requirements (part 1/3) iso 7637-2: 2004(e) test pulse test levels (1) 1. the above test levels must be considered referred to v s = 13.5 v except for pulse 5b. number of pulses or test times burst cycle / pulse repetition time delays and impedance iii iv min. max. 1 -75v -100v 5000 pulses 0.5s 5s 2 ms, 10 ? 2a +37v +50v 5000 pulses 0.2s 5s 50s, 2 ? 3a -100v -150v 1h 90ms 100ms 0.1s, 50 ? 3b +75v +100v 1h 90ms 100ms 0.1s, 50 ? 4 -6v -7v 1 pulse 100ms, 0.01 ? 5b (2) 2. valid in case of external load dump clamp: 40v maximum referred to ground (-40c < t j < 150c). +65v +87v 1 pulse 400ms, 2 ? table 27. electrical transient requirements (part 2/3) iso 7637-2: 2004e test pulse test level results iii vi 1e e 2a c c 3a c c 3b c c table 25. electrical characteristics (out1 - out8) (continued) symbol parameter test condition min. typ. max. unit electrical specifications L99CL01XP 52/60 docid023902 rev 4 4c c 5b (1) cc 1. valid in case of external load dump clamp: 40v maximum referred to ground (-40c < t j < 150c). table 28. electrical transient requirements (part 3/3) class contents c all functions of the device performed as designed after exposure to disturbance. e one or more functions of the device did not perform as designed after exposure to disturbance and cannot be returned to prop er operation without replacing the device. table 27. electrical transient re quirements (part 2/3) (continued) iso 7637-2: 2004e test pulse test level results iii vi docid023902 rev 4 53/60 L99CL01XP package and pcb thermal data 5 package and pcb thermal data 5.1 powersso-36 thermal data figure 9. powersso-36 pc board note: board finish thickness 1.6 mm +/- 10%; board double layer and fo ur layers; board dimension 129x60; board material fr4; cu thickness 0.070 mm (outer layers); cu thickness 0.035 mm (inner layers); thermal vias separation 1.2 mm; thermal via diameter 0.3 mm +/- 0.08 mm; cu thickness on vi as 0.025 mm; footprint dimension 4.1 mm x 6.5 mm package and pcb thermal data L99CL01XP 54/60 docid023902 rev 4 figure 10. r thj-amb vs pcb copper area in open box free air condition (one channel on) 2 4 ( j a m b 2 4 ( j a m b 2 4 ( j ? a m b # 7 0 # " # u h e a t s i n k a r e a c m > ' ! 0 ' # & 4 docid023902 rev 4 55/60 L99CL01XP package information 6 package information 6.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. package information L99CL01XP 56/60 docid023902 rev 4 6.2 powersso-36? mechanical data figure 11. powersso-36? package dimensions ( " 1 ( $ ' 5 docid023902 rev 4 57/60 L99CL01XP package information l table 29. powersso-36? mechanical data symbol millimeters min typ max a 2.15 ? 2.45 a2 2.15 ? 2.35 a1 0 ? 0.1 b 0.18 ? 0.36 c 0.23 ? 0.32 d 10.10 ? 10.50 e7.4?7.6 e?0.5? e3 ? 8.5 ? f?2.3? g??0.1 h 10.1 ? 10.5 h??0.4 k0?8 l 0.55 ? 0.85 m?4.3? n ? - 10 o?1.2? q?0.8? s?2.9? t ? 3.65 ? u?1.0? x (1) 1. corresponding to internal variation c. 4.3 ? 5.2 y (1) 6.9 ? 7.5 package information L99CL01XP 58/60 docid023902 rev 4 6.3 packing information figure 12. powersso-36 tube shipment (no suffix) figure 13. powersso-36 tape and reel shipment (suffix ?tr?) a c b all dimensions are in mm. base q.ty 49 bulk q.ty 1225 tube length ( 0.5) 532 a 3.5 b 13.8 c ( 0.1) 0.6 base q.ty 1000 bulk q.ty 1000 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 24.4 n (min) 100 t (max) 30.4 reel dimensions tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb 1986 all dimensions are in mm. tape width w 24 tape hole spacing p0 ( 0.1) 4 component spacing p 12 hole diameter d ( 0.05) 1.55 hole diameter d1 (min) 1.5 hole position f ( 0.1) 11.5 compartment depth k (max) 2.85 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed docid023902 rev 4 59/60 L99CL01XP revision history 7 revision history table 30. document revision history date revision changes 08-nov-2012 1 initial release. 03-dec-2012 2 table 19: temperature warning and thermal shutdown : ? added note table 21: digital timings : ? added note table 22: electrical characteristics (logic + inputs) : ?f clk fail low : added note table 23: dynamic characteristics (spi) : ? added note table 24: switching (v s =12v; t j =25c) : ?t d(on) , t d(off) , t skew : updated max. value table 25: electrical characteristics (out1 - out8) : ?i cs_offset , i cs_drift_ratio : updated values ? ? k lron , ? k hron : added rows 24-apr-2013 3 updated features list updated section 1.1: power supply (vs, gnd) and section 2.3: current sense (cs) ? analog diagnosis removed figure 4: typical output voltage waveforms (rising/falling edge) updated introduction of chapter 3: spi interface updated table 13: sdr registers updated section : address #12 silicon version updated table 20: thermal data table 22: electrical characteristics (logic + inputs) : ?v porh , v porl : updated parameter and values ?t dsense1h , ? k lron , ? k hron : updated values ?k 0 , dk 0 /k 0 : removed rows added figure 10: r thj-amb vs pcb copper area in open box free air condition (one channel on) 19-sep-2013 4 updated disclaimer. L99CL01XP 60/60 docid023902 rev 4 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particul ar purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ? automotive, automotive safe ty or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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